Fitter report for V1 Wed Oct 21 16:40:50 2026 Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Fitter Summary 3. Fitter Settings 4. Parallel Compilation 5. Ignored Assignments 6. Incremental Compilation Preservation Summary 7. Incremental Compilation Partition Settings 8. Incremental Compilation Placement Preservation 9. Pin-Out File 10. Fitter Resource Usage Summary 11. Fitter Partition Statistics 12. Input Pins 13. Output Pins 14. I/O Bank Usage 15. All Package Pins 16. Output Pin Default Load For Reported TCO 17. Fitter Resource Utilization by Entity 18. Delay Chain Summary 19. Pad To Core Delay Chain Fanout 20. Non-Global High Fan-Out Signals 21. Other Routing Usage Summary 22. LAB Logic Elements 23. LAB Signals Sourced 24. LAB Signals Sourced Out 25. LAB Distinct Inputs 26. Fitter Device Options 27. Operating Settings and Conditions 28. Fitter Messages 29. Fitter Suppressed Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. +---------------------------------------------------------------------------------------+ ; Fitter Summary ; +------------------------------------+--------------------------------------------------+ ; Fitter Status ; Successful - Wed Oct 21 16:40:49 2026 ; ; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version ; ; Revision Name ; V1 ; ; Top-level Entity Name ; 7seg_sw_hex ; ; Family ; Cyclone II ; ; Device ; EP2C20F484C7 ; ; Timing Models ; Final ; ; Total logic elements ; 7 / 18,752 ( < 1 % ) ; ; Total combinational functions ; 7 / 18,752 ( < 1 % ) ; ; Dedicated logic registers ; 0 / 18,752 ( 0 % ) ; ; Total registers ; 0 ; ; Total pins ; 11 / 315 ( 3 % ) ; ; Total virtual pins ; 0 ; ; Total memory bits ; 0 / 239,616 ( 0 % ) ; ; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ; ; Total PLLs ; 0 / 4 ( 0 % ) ; +------------------------------------+--------------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------------------------+ ; Fitter Settings ; +----------------------------------------------------------------------------+--------------------------------+--------------------------------+ ; Option ; Setting ; Default Value ; +----------------------------------------------------------------------------+--------------------------------+--------------------------------+ ; Device ; EP2C20F484C7 ; ; ; Minimum Core Junction Temperature ; 0 ; ; ; Maximum Core Junction Temperature ; 85 ; ; ; Fit Attempts to Skip ; 0 ; 0.0 ; ; Use smart compilation ; Off ; Off ; ; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; ; Enable compact report table ; Off ; Off ; ; Auto Merge PLLs ; On ; On ; ; Ignore PLL Mode When Merging PLLs ; Off ; Off ; ; Router Timing Optimization Level ; Normal ; Normal ; ; Placement Effort Multiplier ; 1.0 ; 1.0 ; ; Router Effort Multiplier ; 1.0 ; 1.0 ; ; Always Enable Input Buffers ; Off ; Off ; ; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ; ; Optimize Multi-Corner Timing ; On ; On ; ; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; ; Optimize Timing ; Normal compilation ; Normal compilation ; ; Optimize Timing for ECOs ; Off ; Off ; ; Regenerate full fit report during ECO compiles ; Off ; Off ; ; Optimize IOC Register Placement for Timing ; Normal ; Normal ; ; Limit to One Fitting Attempt ; Off ; Off ; ; Final Placement Optimizations ; Automatically ; Automatically ; ; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; ; Fitter Initial Placement Seed ; 1 ; 1 ; ; PCI I/O ; Off ; Off ; ; Weak Pull-Up Resistor ; Off ; Off ; ; Enable Bus-Hold Circuitry ; Off ; Off ; ; Auto Global Memory Control Signals ; Off ; Off ; ; Auto Packed Registers ; Auto ; Auto ; ; Auto Delay Chains ; On ; On ; ; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; ; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; ; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; ; Perform Register Duplication for Performance ; Off ; Off ; ; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; ; Perform Register Retiming for Performance ; Off ; Off ; ; Perform Asynchronous Signal Pipelining ; Off ; Off ; ; Fitter Effort ; Auto Fit ; Auto Fit ; ; Physical Synthesis Effort Level ; Normal ; Normal ; ; Auto Global Clock ; On ; On ; ; Auto Global Register Control Signals ; On ; On ; ; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +----------------------------------------------------------------------------+--------------------------------+--------------------------------+ +------------------------------------------+ ; Parallel Compilation ; +----------------------------+-------------+ ; Processors ; Number ; +----------------------------+-------------+ ; Number detected on machine ; 4 ; ; Maximum allowed ; 2 ; ; ; ; ; Average used ; 1.00 ; ; Maximum used ; 2 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; ; Processor 2 ; < 0.1% ; ; Processors 3-4 ; 0.0% ; +----------------------------+-------------+ +---------------------------------------------------------------------------------------------------------+ ; Ignored Assignments ; +----------------------+----------------+--------------+---------------+-----------------+----------------+ ; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ; +----------------------+----------------+--------------+---------------+-----------------+----------------+ ; Location ; ; ; AUD_ADCDAT ; PIN_B6 ; QSF Assignment ; ; Location ; ; ; AUD_ADCLRCK ; PIN_A6 ; QSF Assignment ; ; Location ; ; ; AUD_BCLK ; PIN_A4 ; QSF Assignment ; ; Location ; ; ; AUD_DACDAT ; PIN_B5 ; QSF Assignment ; ; Location ; ; ; AUD_DACLRCK ; PIN_A5 ; QSF Assignment ; ; Location ; ; ; AUD_XCK ; PIN_B4 ; QSF Assignment ; ; Location ; ; ; CLOCK_24[0] ; PIN_B12 ; QSF Assignment ; ; Location ; ; ; CLOCK_24[1] ; PIN_A12 ; QSF Assignment ; ; Location ; ; ; CLOCK_27[0] ; PIN_D12 ; QSF Assignment ; ; Location ; ; ; CLOCK_27[1] ; PIN_E12 ; QSF Assignment ; ; Location ; ; ; CLOCK_50 ; PIN_L1 ; QSF Assignment ; ; Location ; ; ; DRAM_ADDR[0] ; PIN_W4 ; QSF Assignment ; ; Location ; ; ; DRAM_ADDR[10] ; PIN_W3 ; QSF Assignment ; ; Location ; ; ; DRAM_ADDR[11] ; PIN_N6 ; QSF Assignment ; ; Location ; ; ; DRAM_ADDR[1] ; PIN_W5 ; QSF Assignment ; ; Location ; ; ; DRAM_ADDR[2] ; PIN_Y3 ; QSF Assignment ; ; Location ; ; ; DRAM_ADDR[3] ; PIN_Y4 ; QSF Assignment ; ; Location ; ; ; DRAM_ADDR[4] ; PIN_R6 ; QSF Assignment ; ; Location ; ; ; DRAM_ADDR[5] ; PIN_R5 ; QSF Assignment ; ; Location ; ; ; DRAM_ADDR[6] ; PIN_P6 ; QSF Assignment ; ; Location ; ; ; DRAM_ADDR[7] ; PIN_P5 ; QSF Assignment ; ; Location ; ; ; DRAM_ADDR[8] ; PIN_P3 ; QSF Assignment ; ; Location ; ; ; DRAM_ADDR[9] ; PIN_N4 ; QSF Assignment ; ; Location ; ; ; DRAM_BA_0 ; PIN_U3 ; QSF Assignment ; ; Location ; ; ; DRAM_BA_1 ; PIN_V4 ; QSF Assignment ; ; Location ; ; ; DRAM_CAS_N ; PIN_T3 ; QSF Assignment ; ; Location ; ; ; DRAM_CKE ; PIN_N3 ; QSF Assignment ; ; Location ; ; ; DRAM_CLK ; PIN_U4 ; QSF Assignment ; ; Location ; ; ; DRAM_CS_N ; PIN_T6 ; QSF Assignment ; ; Location ; ; ; DRAM_DQ[0] ; PIN_U1 ; QSF Assignment ; ; Location ; ; ; DRAM_DQ[10] ; PIN_P1 ; QSF Assignment ; ; Location ; ; ; DRAM_DQ[11] ; PIN_P2 ; QSF Assignment ; ; Location ; ; ; DRAM_DQ[12] ; PIN_R1 ; QSF Assignment ; ; Location ; ; ; DRAM_DQ[13] ; PIN_R2 ; QSF Assignment ; ; Location ; ; ; DRAM_DQ[14] ; PIN_T1 ; QSF Assignment ; ; Location ; ; ; DRAM_DQ[15] ; PIN_T2 ; QSF Assignment ; ; Location ; ; ; DRAM_DQ[1] ; PIN_U2 ; QSF Assignment ; ; Location ; ; ; DRAM_DQ[2] ; PIN_V1 ; QSF Assignment ; ; Location ; ; ; DRAM_DQ[3] ; PIN_V2 ; QSF Assignment ; ; Location ; ; ; DRAM_DQ[4] ; PIN_W1 ; QSF Assignment ; ; Location ; ; ; DRAM_DQ[5] ; PIN_W2 ; QSF Assignment ; ; Location ; ; ; DRAM_DQ[6] ; PIN_Y1 ; QSF Assignment ; ; Location ; ; ; DRAM_DQ[7] ; PIN_Y2 ; QSF Assignment ; ; Location ; ; ; DRAM_DQ[8] ; PIN_N1 ; QSF Assignment ; ; Location ; ; ; DRAM_DQ[9] ; PIN_N2 ; QSF Assignment ; ; Location ; ; ; DRAM_LDQM ; PIN_R7 ; QSF Assignment ; ; Location ; ; ; DRAM_RAS_N ; PIN_T5 ; QSF Assignment ; ; Location ; ; ; DRAM_UDQM ; PIN_M5 ; QSF Assignment ; ; Location ; ; ; DRAM_WE_N ; PIN_R8 ; QSF Assignment ; ; Location ; ; ; EXT_CLOCK ; PIN_M21 ; QSF Assignment ; ; Location ; ; ; FL_ADDR[0] ; PIN_AB20 ; QSF Assignment ; ; Location ; ; ; FL_ADDR[10] ; PIN_R12 ; QSF Assignment ; ; Location ; ; ; FL_ADDR[11] ; PIN_T12 ; QSF Assignment ; ; Location ; ; ; FL_ADDR[12] ; PIN_AB14 ; QSF Assignment ; ; Location ; ; ; FL_ADDR[13] ; PIN_AA13 ; QSF Assignment ; ; Location ; ; ; FL_ADDR[14] ; PIN_AB13 ; QSF Assignment ; ; Location ; ; ; FL_ADDR[15] ; PIN_AA12 ; QSF Assignment ; ; Location ; ; ; FL_ADDR[16] ; PIN_AB12 ; QSF Assignment ; ; Location ; ; ; FL_ADDR[17] ; PIN_AA20 ; QSF Assignment ; ; Location ; ; ; FL_ADDR[18] ; PIN_U14 ; QSF Assignment ; ; Location ; ; ; FL_ADDR[19] ; PIN_V14 ; QSF Assignment ; ; Location ; ; ; FL_ADDR[1] ; PIN_AA14 ; QSF Assignment ; ; Location ; ; ; FL_ADDR[20] ; PIN_U13 ; QSF Assignment ; ; Location ; ; ; FL_ADDR[21] ; PIN_R13 ; QSF Assignment ; ; Location ; ; ; FL_ADDR[2] ; PIN_Y16 ; QSF Assignment ; ; Location ; ; ; FL_ADDR[3] ; PIN_R15 ; QSF Assignment ; ; Location ; ; ; FL_ADDR[4] ; PIN_T15 ; QSF Assignment ; ; Location ; ; ; FL_ADDR[5] ; PIN_U15 ; QSF Assignment ; ; Location ; ; ; FL_ADDR[6] ; PIN_V15 ; QSF Assignment ; ; Location ; ; ; FL_ADDR[7] ; PIN_W15 ; QSF Assignment ; ; Location ; ; ; FL_ADDR[8] ; PIN_R14 ; QSF Assignment ; ; Location ; ; ; FL_ADDR[9] ; PIN_Y13 ; QSF Assignment ; ; Location ; ; ; FL_DQ[0] ; PIN_AB16 ; QSF Assignment ; ; Location ; ; ; FL_DQ[1] ; PIN_AA16 ; QSF Assignment ; ; Location ; ; ; FL_DQ[2] ; PIN_AB17 ; QSF Assignment ; ; Location ; ; ; FL_DQ[3] ; PIN_AA17 ; QSF Assignment ; ; Location ; ; ; FL_DQ[4] ; PIN_AB18 ; QSF Assignment ; ; Location ; ; ; FL_DQ[5] ; PIN_AA18 ; QSF Assignment ; ; Location ; ; ; FL_DQ[6] ; PIN_AB19 ; QSF Assignment ; ; Location ; ; ; FL_DQ[7] ; PIN_AA19 ; QSF Assignment ; ; Location ; ; ; FL_OE_N ; PIN_AA15 ; QSF Assignment ; ; Location ; ; ; FL_RST_N ; PIN_W14 ; QSF Assignment ; ; Location ; ; ; FL_WE_N ; PIN_Y14 ; QSF Assignment ; ; Location ; ; ; GPIO_0[0] ; PIN_A13 ; QSF Assignment ; ; Location ; ; ; GPIO_0[10] ; PIN_A18 ; QSF Assignment ; ; Location ; ; ; GPIO_0[11] ; PIN_B18 ; QSF Assignment ; ; Location ; ; ; GPIO_0[12] ; PIN_A19 ; QSF Assignment ; ; Location ; ; ; GPIO_0[13] ; PIN_B19 ; QSF Assignment ; ; Location ; ; ; GPIO_0[14] ; PIN_A20 ; QSF Assignment ; ; Location ; ; ; GPIO_0[15] ; PIN_B20 ; QSF Assignment ; ; Location ; ; ; GPIO_0[16] ; PIN_C21 ; QSF Assignment ; ; Location ; ; ; GPIO_0[17] ; PIN_C22 ; QSF Assignment ; ; Location ; ; ; GPIO_0[18] ; PIN_D21 ; QSF Assignment ; ; Location ; ; ; GPIO_0[19] ; PIN_D22 ; QSF Assignment ; ; Location ; ; ; GPIO_0[1] ; PIN_B13 ; QSF Assignment ; ; Location ; ; ; GPIO_0[20] ; PIN_E21 ; QSF Assignment ; ; Location ; ; ; GPIO_0[21] ; PIN_E22 ; QSF Assignment ; ; Location ; ; ; GPIO_0[22] ; PIN_F21 ; QSF Assignment ; ; Location ; ; ; GPIO_0[23] ; PIN_F22 ; QSF Assignment ; ; Location ; ; ; GPIO_0[24] ; PIN_G21 ; QSF Assignment ; ; Location ; ; ; GPIO_0[25] ; PIN_G22 ; QSF Assignment ; ; Location ; ; ; GPIO_0[26] ; PIN_J21 ; QSF Assignment ; ; Location ; ; ; GPIO_0[27] ; PIN_J22 ; QSF Assignment ; ; Location ; ; ; GPIO_0[28] ; PIN_K21 ; QSF Assignment ; ; Location ; ; ; GPIO_0[29] ; PIN_K22 ; QSF Assignment ; ; Location ; ; ; GPIO_0[2] ; PIN_A14 ; QSF Assignment ; ; Location ; ; ; GPIO_0[30] ; PIN_J19 ; QSF Assignment ; ; Location ; ; ; GPIO_0[31] ; PIN_J20 ; QSF Assignment ; ; Location ; ; ; GPIO_0[32] ; PIN_J18 ; QSF Assignment ; ; Location ; ; ; GPIO_0[33] ; PIN_K20 ; QSF Assignment ; ; Location ; ; ; GPIO_0[34] ; PIN_L19 ; QSF Assignment ; ; Location ; ; ; GPIO_0[35] ; PIN_L18 ; QSF Assignment ; ; Location ; ; ; GPIO_0[3] ; PIN_B14 ; QSF Assignment ; ; Location ; ; ; GPIO_0[4] ; PIN_A15 ; QSF Assignment ; ; Location ; ; ; GPIO_0[5] ; PIN_B15 ; QSF Assignment ; ; Location ; ; ; GPIO_0[6] ; PIN_A16 ; QSF Assignment ; ; Location ; ; ; GPIO_0[7] ; PIN_B16 ; QSF Assignment ; ; Location ; ; ; GPIO_0[8] ; PIN_A17 ; QSF Assignment ; ; Location ; ; ; GPIO_0[9] ; PIN_B17 ; QSF Assignment ; ; Location ; ; ; GPIO_1[0] ; PIN_H12 ; QSF Assignment ; ; Location ; ; ; GPIO_1[10] ; PIN_C14 ; QSF Assignment ; ; Location ; ; ; GPIO_1[11] ; PIN_D14 ; QSF Assignment ; ; Location ; ; ; GPIO_1[12] ; PIN_D15 ; QSF Assignment ; ; Location ; ; ; GPIO_1[13] ; PIN_D16 ; QSF Assignment ; ; Location ; ; ; GPIO_1[14] ; PIN_C17 ; QSF Assignment ; ; Location ; ; ; GPIO_1[15] ; PIN_C18 ; QSF Assignment ; ; Location ; ; ; GPIO_1[16] ; PIN_C19 ; QSF Assignment ; ; Location ; ; ; GPIO_1[17] ; PIN_C20 ; QSF Assignment ; ; Location ; ; ; GPIO_1[18] ; PIN_D19 ; QSF Assignment ; ; Location ; ; ; GPIO_1[19] ; PIN_D20 ; QSF Assignment ; ; Location ; ; ; GPIO_1[1] ; PIN_H13 ; QSF Assignment ; ; Location ; ; ; GPIO_1[20] ; PIN_E20 ; QSF Assignment ; ; Location ; ; ; GPIO_1[21] ; PIN_F20 ; QSF Assignment ; ; Location ; ; ; GPIO_1[22] ; PIN_E19 ; QSF Assignment ; ; Location ; ; ; GPIO_1[23] ; PIN_E18 ; QSF Assignment ; ; Location ; ; ; GPIO_1[24] ; PIN_G20 ; QSF Assignment ; ; Location ; ; ; GPIO_1[25] ; PIN_G18 ; QSF Assignment ; ; Location ; ; ; GPIO_1[26] ; PIN_G17 ; QSF Assignment ; ; Location ; ; ; GPIO_1[27] ; PIN_H17 ; QSF Assignment ; ; Location ; ; ; GPIO_1[28] ; PIN_J15 ; QSF Assignment ; ; Location ; ; ; GPIO_1[29] ; PIN_H18 ; QSF Assignment ; ; Location ; ; ; GPIO_1[2] ; PIN_H14 ; QSF Assignment ; ; Location ; ; ; GPIO_1[30] ; PIN_N22 ; QSF Assignment ; ; Location ; ; ; GPIO_1[31] ; PIN_N21 ; QSF Assignment ; ; Location ; ; ; GPIO_1[32] ; PIN_P15 ; QSF Assignment ; ; Location ; ; ; GPIO_1[33] ; PIN_N15 ; QSF Assignment ; ; Location ; ; ; GPIO_1[34] ; PIN_P17 ; QSF Assignment ; ; Location ; ; ; GPIO_1[35] ; PIN_P18 ; QSF Assignment ; ; Location ; ; ; GPIO_1[3] ; PIN_G15 ; QSF Assignment ; ; Location ; ; ; GPIO_1[4] ; PIN_E14 ; QSF Assignment ; ; Location ; ; ; GPIO_1[5] ; PIN_E15 ; QSF Assignment ; ; Location ; ; ; GPIO_1[6] ; PIN_F15 ; QSF Assignment ; ; Location ; ; ; GPIO_1[7] ; PIN_G16 ; QSF Assignment ; ; Location ; ; ; GPIO_1[8] ; PIN_F12 ; QSF Assignment ; ; Location ; ; ; GPIO_1[9] ; PIN_F13 ; QSF Assignment ; ; Location ; ; ; HEX1[0] ; PIN_E1 ; QSF Assignment ; ; Location ; ; ; HEX1[1] ; PIN_H6 ; QSF Assignment ; ; Location ; ; ; HEX1[2] ; PIN_H5 ; QSF Assignment ; ; Location ; ; ; HEX1[3] ; PIN_H4 ; QSF Assignment ; ; Location ; ; ; HEX1[4] ; PIN_G3 ; QSF Assignment ; ; Location ; ; ; HEX1[5] ; PIN_D2 ; QSF Assignment ; ; Location ; ; ; HEX1[6] ; PIN_D1 ; QSF Assignment ; ; Location ; ; ; HEX2[0] ; PIN_G5 ; QSF Assignment ; ; Location ; ; ; HEX2[1] ; PIN_G6 ; QSF Assignment ; ; Location ; ; ; HEX2[2] ; PIN_C2 ; QSF Assignment ; ; Location ; ; ; HEX2[3] ; PIN_C1 ; QSF Assignment ; ; Location ; ; ; HEX2[4] ; PIN_E3 ; QSF Assignment ; ; Location ; ; ; HEX2[5] ; PIN_E4 ; QSF Assignment ; ; Location ; ; ; HEX2[6] ; PIN_D3 ; QSF Assignment ; ; Location ; ; ; HEX3[0] ; PIN_F4 ; QSF Assignment ; ; Location ; ; ; HEX3[1] ; PIN_D5 ; QSF Assignment ; ; Location ; ; ; HEX3[2] ; PIN_D6 ; QSF Assignment ; ; Location ; ; ; HEX3[3] ; PIN_J4 ; QSF Assignment ; ; Location ; ; ; HEX3[4] ; PIN_L8 ; QSF Assignment ; ; Location ; ; ; HEX3[5] ; PIN_F3 ; QSF Assignment ; ; Location ; ; ; HEX3[6] ; PIN_D4 ; QSF Assignment ; ; Location ; ; ; I2C_SCLK ; PIN_A3 ; QSF Assignment ; ; Location ; ; ; I2C_SDAT ; PIN_B3 ; QSF Assignment ; ; Location ; ; ; KEY[0] ; PIN_R22 ; QSF Assignment ; ; Location ; ; ; KEY[1] ; PIN_R21 ; QSF Assignment ; ; Location ; ; ; KEY[2] ; PIN_T22 ; QSF Assignment ; ; Location ; ; ; KEY[3] ; PIN_T21 ; QSF Assignment ; ; Location ; ; ; LEDG[0] ; PIN_U22 ; QSF Assignment ; ; Location ; ; ; LEDG[1] ; PIN_U21 ; QSF Assignment ; ; Location ; ; ; LEDG[2] ; PIN_V22 ; QSF Assignment ; ; Location ; ; ; LEDG[3] ; PIN_V21 ; QSF Assignment ; ; Location ; ; ; LEDG[4] ; PIN_W22 ; QSF Assignment ; ; Location ; ; ; LEDG[5] ; PIN_W21 ; QSF Assignment ; ; Location ; ; ; LEDG[6] ; PIN_Y22 ; QSF Assignment ; ; Location ; ; ; LEDG[7] ; PIN_Y21 ; QSF Assignment ; ; Location ; ; ; LEDR[0] ; PIN_R20 ; QSF Assignment ; ; Location ; ; ; LEDR[1] ; PIN_R19 ; QSF Assignment ; ; Location ; ; ; LEDR[2] ; PIN_U19 ; QSF Assignment ; ; Location ; ; ; LEDR[3] ; PIN_Y19 ; QSF Assignment ; ; Location ; ; ; LEDR[4] ; PIN_T18 ; QSF Assignment ; ; Location ; ; ; LEDR[5] ; PIN_V19 ; QSF Assignment ; ; Location ; ; ; LEDR[6] ; PIN_Y18 ; QSF Assignment ; ; Location ; ; ; LEDR[7] ; PIN_U18 ; QSF Assignment ; ; Location ; ; ; LEDR[8] ; PIN_R18 ; QSF Assignment ; ; Location ; ; ; LEDR[9] ; PIN_R17 ; QSF Assignment ; ; Location ; ; ; PS2_CLK ; PIN_H15 ; QSF Assignment ; ; Location ; ; ; PS2_DAT ; PIN_J14 ; QSF Assignment ; ; Location ; ; ; SD_CLK ; PIN_V20 ; QSF Assignment ; ; Location ; ; ; SD_CMD ; PIN_Y20 ; QSF Assignment ; ; Location ; ; ; SD_DAT ; PIN_W20 ; QSF Assignment ; ; Location ; ; ; SD_DAT3 ; PIN_U20 ; QSF Assignment ; ; Location ; ; ; SRAM_ADDR[0] ; PIN_AA3 ; QSF Assignment ; ; Location ; ; ; SRAM_ADDR[10] ; PIN_R11 ; QSF Assignment ; ; Location ; ; ; SRAM_ADDR[11] ; PIN_T11 ; QSF Assignment ; ; Location ; ; ; SRAM_ADDR[12] ; PIN_Y10 ; QSF Assignment ; ; Location ; ; ; SRAM_ADDR[13] ; PIN_U10 ; QSF Assignment ; ; Location ; ; ; SRAM_ADDR[14] ; PIN_R10 ; QSF Assignment ; ; Location ; ; ; SRAM_ADDR[15] ; PIN_T7 ; QSF Assignment ; ; Location ; ; ; SRAM_ADDR[16] ; PIN_Y6 ; QSF Assignment ; ; Location ; ; ; SRAM_ADDR[17] ; PIN_Y5 ; QSF Assignment ; ; Location ; ; ; SRAM_ADDR[1] ; PIN_AB3 ; QSF Assignment ; ; Location ; ; ; SRAM_ADDR[2] ; PIN_AA4 ; QSF Assignment ; ; Location ; ; ; SRAM_ADDR[3] ; PIN_AB4 ; QSF Assignment ; ; Location ; ; ; SRAM_ADDR[4] ; PIN_AA5 ; QSF Assignment ; ; Location ; ; ; SRAM_ADDR[5] ; PIN_AB10 ; QSF Assignment ; ; Location ; ; ; SRAM_ADDR[6] ; PIN_AA11 ; QSF Assignment ; ; Location ; ; ; SRAM_ADDR[7] ; PIN_AB11 ; QSF Assignment ; ; Location ; ; ; SRAM_ADDR[8] ; PIN_V11 ; QSF Assignment ; ; Location ; ; ; SRAM_ADDR[9] ; PIN_W11 ; QSF Assignment ; ; Location ; ; ; SRAM_CE_N ; PIN_AB5 ; QSF Assignment ; ; Location ; ; ; SRAM_DQ[0] ; PIN_AA6 ; QSF Assignment ; ; Location ; ; ; SRAM_DQ[10] ; PIN_V9 ; QSF Assignment ; ; Location ; ; ; SRAM_DQ[11] ; PIN_U9 ; QSF Assignment ; ; Location ; ; ; SRAM_DQ[12] ; PIN_R9 ; QSF Assignment ; ; Location ; ; ; SRAM_DQ[13] ; PIN_W8 ; QSF Assignment ; ; Location ; ; ; SRAM_DQ[14] ; PIN_V8 ; QSF Assignment ; ; Location ; ; ; SRAM_DQ[15] ; PIN_U8 ; QSF Assignment ; ; Location ; ; ; SRAM_DQ[1] ; PIN_AB6 ; QSF Assignment ; ; Location ; ; ; SRAM_DQ[2] ; PIN_AA7 ; QSF Assignment ; ; Location ; ; ; SRAM_DQ[3] ; PIN_AB7 ; QSF Assignment ; ; Location ; ; ; SRAM_DQ[4] ; PIN_AA8 ; QSF Assignment ; ; Location ; ; ; SRAM_DQ[5] ; PIN_AB8 ; QSF Assignment ; ; Location ; ; ; SRAM_DQ[6] ; PIN_AA9 ; QSF Assignment ; ; Location ; ; ; SRAM_DQ[7] ; PIN_AB9 ; QSF Assignment ; ; Location ; ; ; SRAM_DQ[8] ; PIN_Y9 ; QSF Assignment ; ; Location ; ; ; SRAM_DQ[9] ; PIN_W9 ; QSF Assignment ; ; Location ; ; ; SRAM_LB_N ; PIN_Y7 ; QSF Assignment ; ; Location ; ; ; SRAM_OE_N ; PIN_T8 ; QSF Assignment ; ; Location ; ; ; SRAM_UB_N ; PIN_W7 ; QSF Assignment ; ; Location ; ; ; SRAM_WE_N ; PIN_AA10 ; QSF Assignment ; ; Location ; ; ; SW[4] ; PIN_W12 ; QSF Assignment ; ; Location ; ; ; SW[5] ; PIN_U12 ; QSF Assignment ; ; Location ; ; ; SW[6] ; PIN_U11 ; QSF Assignment ; ; Location ; ; ; SW[7] ; PIN_M2 ; QSF Assignment ; ; Location ; ; ; SW[8] ; PIN_M1 ; QSF Assignment ; ; Location ; ; ; SW[9] ; PIN_L2 ; QSF Assignment ; ; Location ; ; ; TCK ; PIN_C7 ; QSF Assignment ; ; Location ; ; ; TCS ; PIN_D8 ; QSF Assignment ; ; Location ; ; ; TDI ; PIN_E8 ; QSF Assignment ; ; Location ; ; ; TDO ; PIN_D7 ; QSF Assignment ; ; Location ; ; ; UART_RXD ; PIN_F14 ; QSF Assignment ; ; Location ; ; ; UART_TXD ; PIN_G12 ; QSF Assignment ; ; Location ; ; ; VGA_B[0] ; PIN_A9 ; QSF Assignment ; ; Location ; ; ; VGA_B[1] ; PIN_D11 ; QSF Assignment ; ; Location ; ; ; VGA_B[2] ; PIN_A10 ; QSF Assignment ; ; Location ; ; ; VGA_B[3] ; PIN_B10 ; QSF Assignment ; ; Location ; ; ; VGA_G[0] ; PIN_B8 ; QSF Assignment ; ; Location ; ; ; VGA_G[1] ; PIN_C10 ; QSF Assignment ; ; Location ; ; ; VGA_G[2] ; PIN_B9 ; QSF Assignment ; ; Location ; ; ; VGA_G[3] ; PIN_A8 ; QSF Assignment ; ; Location ; ; ; VGA_HS ; PIN_A11 ; QSF Assignment ; ; Location ; ; ; VGA_R[0] ; PIN_D9 ; QSF Assignment ; ; Location ; ; ; VGA_R[1] ; PIN_C9 ; QSF Assignment ; ; Location ; ; ; VGA_R[2] ; PIN_A7 ; QSF Assignment ; ; Location ; ; ; VGA_R[3] ; PIN_B7 ; QSF Assignment ; ; Location ; ; ; VGA_VS ; PIN_B11 ; QSF Assignment ; ; I/O Standard ; ; ; AUD_ADCDAT ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; AUD_ADCLRCK ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; AUD_BCLK ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; AUD_DACDAT ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; AUD_DACLRCK ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; AUD_XCK ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; CLOCK_24[0] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; CLOCK_24[1] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; CLOCK_27[1] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; CLOCK_50 ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; EXT_CLOCK ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_0[0] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_0[10] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_0[11] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_0[12] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_0[13] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_0[14] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_0[15] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_0[16] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_0[17] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_0[18] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_0[19] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_0[1] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_0[20] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_0[21] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_0[22] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_0[23] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_0[24] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_0[25] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_0[26] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_0[27] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_0[28] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_0[29] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_0[2] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_0[30] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_0[31] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_0[32] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_0[33] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_0[34] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_0[35] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_0[3] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_0[4] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_0[5] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_0[6] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_0[7] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_0[8] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_0[9] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_1[0] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_1[10] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_1[11] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_1[12] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_1[13] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_1[14] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_1[15] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_1[16] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_1[17] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_1[18] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_1[19] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_1[1] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_1[20] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_1[21] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_1[22] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_1[23] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_1[24] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_1[25] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_1[26] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_1[27] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_1[28] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_1[29] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_1[2] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_1[30] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_1[31] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_1[32] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_1[33] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_1[34] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_1[35] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_1[3] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_1[4] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_1[5] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_1[6] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_1[7] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_1[8] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; GPIO_1[9] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; HEX1[0] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; HEX1[1] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; HEX1[2] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; HEX1[3] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; HEX1[4] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; HEX1[5] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; HEX1[6] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; HEX2[0] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; HEX2[1] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; HEX2[2] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; HEX2[3] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; HEX2[4] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; HEX2[5] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; HEX2[6] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; HEX3[0] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; HEX3[1] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; HEX3[2] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; HEX3[3] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; HEX3[4] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; HEX3[5] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; HEX3[6] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; I2C_SCLK ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; I2C_SDAT ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; KEY[0] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; KEY[1] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; KEY[2] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; KEY[3] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; LEDG[0] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; LEDG[1] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; LEDG[2] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; LEDG[3] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; LEDG[4] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; LEDG[5] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; LEDG[6] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; LEDG[7] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; LEDR[0] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; LEDR[1] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; LEDR[2] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; LEDR[3] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; LEDR[4] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; LEDR[5] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; LEDR[6] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; LEDR[7] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; LEDR[8] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; LEDR[9] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; PS2_CLK ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; PS2_DAT ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; SW[4] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; SW[5] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; SW[6] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; SW[7] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; SW[8] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; SW[9] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; TCK ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; TCS ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; TDI ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; TDO ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; UART_RXD ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; UART_TXD ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; VGA_B[0] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; VGA_B[1] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; VGA_B[2] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; VGA_B[3] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; VGA_G[0] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; VGA_G[1] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; VGA_G[2] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; VGA_G[3] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; VGA_HS ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; VGA_R[0] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; VGA_R[1] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; VGA_R[2] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; VGA_R[3] ; LVTTL ; QSF Assignment ; ; I/O Standard ; ; ; VGA_VS ; LVTTL ; QSF Assignment ; ; Fast Input Register ; 7seg_sw_hex ; ; * ; ON ; QSF Assignment ; ; Fast Output Register ; 7seg_sw_hex ; ; * ; ON ; QSF Assignment ; ; Current Strength ; 7seg_sw_hex ; ; I2C_SCLK ; MAXIMUM CURRENT ; QSF Assignment ; ; Current Strength ; 7seg_sw_hex ; ; I2C_SDAT ; MAXIMUM CURRENT ; QSF Assignment ; +----------------------+----------------+--------------+---------------+-----------------+----------------+ +----------------------------------------------+ ; Incremental Compilation Preservation Summary ; +---------------------+------------------------+ ; Type ; Value ; +---------------------+------------------------+ ; Placement (by node) ; ; ; -- Requested ; 0 / 22 ( 0.00 % ) ; ; -- Achieved ; 0 / 22 ( 0.00 % ) ; ; ; ; ; Routing (by net) ; ; ; -- Requested ; 0 / 0 ( 0.00 % ) ; ; -- Achieved ; 0 / 0 ( 0.00 % ) ; +---------------------+------------------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Incremental Compilation Partition Settings ; +--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ ; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; +--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ ; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; ; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; +--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +------------------------------------------------------------------------------------------------------------+ ; Incremental Compilation Placement Preservation ; +--------------------------------+---------+-------------------+-------------------------+-------------------+ ; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ; +--------------------------------+---------+-------------------+-------------------------+-------------------+ ; Top ; 19 ; 0 ; N/A ; Source File ; ; hard_block:auto_generated_inst ; 3 ; 0 ; N/A ; Source File ; +--------------------------------+---------+-------------------+-------------------------+-------------------+ +--------------+ ; Pin-Out File ; +--------------+ The pin-out file can be found in /scratch/Versuch 1/output_files/V1.pin. +--------------------------------------------------------------------+ ; Fitter Resource Usage Summary ; +---------------------------------------------+----------------------+ ; Resource ; Usage ; +---------------------------------------------+----------------------+ ; Total logic elements ; 7 / 18,752 ( < 1 % ) ; ; -- Combinational with no register ; 7 ; ; -- Register only ; 0 ; ; -- Combinational with a register ; 0 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; ; -- 4 input functions ; 7 ; ; -- 3 input functions ; 0 ; ; -- <=2 input functions ; 0 ; ; -- Register only ; 0 ; ; ; ; ; Logic elements by mode ; ; ; -- normal mode ; 7 ; ; -- arithmetic mode ; 0 ; ; ; ; ; Total registers* ; 0 / 19,649 ( 0 % ) ; ; -- Dedicated logic registers ; 0 / 18,752 ( 0 % ) ; ; -- I/O registers ; 0 / 897 ( 0 % ) ; ; ; ; ; Total LABs: partially or completely used ; 1 / 1,172 ( < 1 % ) ; ; Virtual pins ; 0 ; ; I/O pins ; 11 / 315 ( 3 % ) ; ; -- Clock pins ; 3 / 8 ( 38 % ) ; ; ; ; ; Global signals ; 0 ; ; M4Ks ; 0 / 52 ( 0 % ) ; ; Total block memory bits ; 0 / 239,616 ( 0 % ) ; ; Total block memory implementation bits ; 0 / 239,616 ( 0 % ) ; ; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ; ; PLLs ; 0 / 4 ( 0 % ) ; ; Global clocks ; 0 / 16 ( 0 % ) ; ; JTAGs ; 0 / 1 ( 0 % ) ; ; ASMI blocks ; 0 / 1 ( 0 % ) ; ; CRC blocks ; 0 / 1 ( 0 % ) ; ; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ; ; Peak interconnect usage (total/H/V) ; 0% / 0% / 0% ; ; Maximum fan-out ; 7 ; ; Highest non-global fan-out ; 7 ; ; Total fan-out ; 35 ; ; Average fan-out ; 1.67 ; +---------------------------------------------+----------------------+ * Register count does not include registers inside RAM blocks or DSP blocks. +----------------------------------------------------------------------------------------------------+ ; Fitter Partition Statistics ; +---------------------------------------------+---------------------+--------------------------------+ ; Statistic ; Top ; hard_block:auto_generated_inst ; +---------------------------------------------+---------------------+--------------------------------+ ; Difficulty Clustering Region ; Low ; Low ; ; ; ; ; ; Total logic elements ; 7 / 18752 ( < 1 % ) ; 0 / 18752 ( 0 % ) ; ; -- Combinational with no register ; 7 ; 0 ; ; -- Register only ; 0 ; 0 ; ; -- Combinational with a register ; 0 ; 0 ; ; ; ; ; ; Logic element usage by number of LUT inputs ; ; ; ; -- 4 input functions ; 7 ; 0 ; ; -- 3 input functions ; 0 ; 0 ; ; -- <=2 input functions ; 0 ; 0 ; ; -- Register only ; 0 ; 0 ; ; ; ; ; ; Logic elements by mode ; ; ; ; -- normal mode ; 7 ; 0 ; ; -- arithmetic mode ; 0 ; 0 ; ; ; ; ; ; Total registers ; 0 ; 0 ; ; -- Dedicated logic registers ; 0 / 18752 ( 0 % ) ; 0 / 18752 ( 0 % ) ; ; ; ; ; ; Total LABs: partially or completely used ; 1 / 1172 ( < 1 % ) ; 0 / 1172 ( 0 % ) ; ; ; ; ; ; Virtual pins ; 0 ; 0 ; ; I/O pins ; 11 ; 0 ; ; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ; 0 / 52 ( 0 % ) ; ; Total memory bits ; 0 ; 0 ; ; Total RAM block bits ; 0 ; 0 ; ; ; ; ; ; Connections ; ; ; ; -- Input Connections ; 0 ; 0 ; ; -- Registered Input Connections ; 0 ; 0 ; ; -- Output Connections ; 0 ; 0 ; ; -- Registered Output Connections ; 0 ; 0 ; ; ; ; ; ; Internal Connections ; ; ; ; -- Total Connections ; 35 ; 0 ; ; -- Registered Connections ; 0 ; 0 ; ; ; ; ; ; External Connections ; ; ; ; -- Top ; 0 ; 0 ; ; -- hard_block:auto_generated_inst ; 0 ; 0 ; ; ; ; ; ; Partition Interface ; ; ; ; -- Input Ports ; 4 ; 0 ; ; -- Output Ports ; 7 ; 0 ; ; -- Bidir Ports ; 0 ; 0 ; ; ; ; ; ; Registered Ports ; ; ; ; -- Registered Input Ports ; 0 ; 0 ; ; -- Registered Output Ports ; 0 ; 0 ; ; ; ; ; ; Port Connectivity ; ; ; ; -- Input Ports driven by GND ; 0 ; 0 ; ; -- Output Ports driven by GND ; 0 ; 0 ; ; -- Input Ports driven by VCC ; 0 ; 0 ; ; -- Output Ports driven by VCC ; 0 ; 0 ; ; -- Input Ports with no Source ; 0 ; 0 ; ; -- Output Ports with no Source ; 0 ; 0 ; ; -- Input Ports with no Fanout ; 0 ; 0 ; ; -- Output Ports with no Fanout ; 0 ; 0 ; +---------------------------------------------+---------------------+--------------------------------+ +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Input Pins ; +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ; +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ ; SW[0] ; L22 ; 5 ; 50 ; 14 ; 0 ; 7 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; ; SW[1] ; L21 ; 5 ; 50 ; 14 ; 1 ; 7 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; ; SW[2] ; M22 ; 6 ; 50 ; 14 ; 2 ; 7 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; ; SW[3] ; V12 ; 7 ; 26 ; 0 ; 0 ; 7 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Output Pins ; +---------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+ ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; +---------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+ ; HEX0[0] ; J2 ; 2 ; 0 ; 18 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 4mA ; Off ; User ; 0 pF ; - ; - ; ; HEX0[1] ; J1 ; 2 ; 0 ; 18 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 4mA ; Off ; User ; 0 pF ; - ; - ; ; HEX0[2] ; H2 ; 2 ; 0 ; 19 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 4mA ; Off ; User ; 0 pF ; - ; - ; ; HEX0[3] ; H1 ; 2 ; 0 ; 19 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 4mA ; Off ; User ; 0 pF ; - ; - ; ; HEX0[4] ; F2 ; 2 ; 0 ; 20 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 4mA ; Off ; User ; 0 pF ; - ; - ; ; HEX0[5] ; F1 ; 2 ; 0 ; 20 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 4mA ; Off ; User ; 0 pF ; - ; - ; ; HEX0[6] ; E2 ; 2 ; 0 ; 20 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 4mA ; Off ; User ; 0 pF ; - ; - ; +---------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+ +-----------------------------------------------------------+ ; I/O Bank Usage ; +----------+-----------------+---------------+--------------+ ; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; +----------+-----------------+---------------+--------------+ ; 1 ; 0 / 41 ( 0 % ) ; 3.3V ; -- ; ; 2 ; 9 / 33 ( 27 % ) ; 3.3V ; -- ; ; 3 ; 0 / 43 ( 0 % ) ; 3.3V ; -- ; ; 4 ; 0 / 40 ( 0 % ) ; 3.3V ; -- ; ; 5 ; 2 / 39 ( 5 % ) ; 3.3V ; -- ; ; 6 ; 2 / 36 ( 6 % ) ; 3.3V ; -- ; ; 7 ; 1 / 40 ( 3 % ) ; 3.3V ; -- ; ; 8 ; 0 / 43 ( 0 % ) ; 3.3V ; -- ; +----------+-----------------+---------------+--------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; All Package Pins ; +----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ ; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; +----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ ; A1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; A2 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; A3 ; 325 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; A4 ; 324 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; A5 ; 322 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; A6 ; 320 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; A7 ; 306 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; A8 ; 304 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; A9 ; 298 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; A10 ; 293 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; A11 ; 287 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; A12 ; 283 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; ; A13 ; 281 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; A14 ; 279 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; A15 ; 273 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; A16 ; 271 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; A17 ; 265 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; A18 ; 251 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; A19 ; 249 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; A20 ; 247 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; A21 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AA1 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AA3 ; 82 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; AA4 ; 85 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; AA5 ; 89 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; AA6 ; 97 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; AA7 ; 103 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; AA8 ; 111 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; AA9 ; 114 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; AA10 ; 120 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; AA11 ; 122 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; AA12 ; 128 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; AA13 ; 130 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; AA14 ; 136 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; AA15 ; 138 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; AA16 ; 140 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; AA17 ; 144 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; AA18 ; 153 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; AA19 ; 162 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; AA20 ; 164 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; AA21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AA22 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AB2 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; AB3 ; 83 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; AB4 ; 84 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; AB5 ; 88 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; AB6 ; 96 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; AB7 ; 102 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; AB8 ; 110 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; AB9 ; 113 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; AB10 ; 119 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; AB11 ; 121 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; AB12 ; 127 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; AB13 ; 129 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; AB14 ; 135 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; AB15 ; 137 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; AB16 ; 139 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; AB17 ; 143 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; AB18 ; 152 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; AB19 ; 161 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; AB20 ; 163 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; AB21 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; AB22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; B1 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; B3 ; 326 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; B4 ; 323 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; B5 ; 321 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; B6 ; 319 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; B7 ; 305 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; B8 ; 303 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; B9 ; 297 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; B10 ; 292 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; B11 ; 286 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; B12 ; 282 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; ; B13 ; 280 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; B14 ; 278 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; B15 ; 272 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; B16 ; 270 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; B17 ; 264 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; B18 ; 250 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; B19 ; 248 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; B20 ; 246 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; B21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; B22 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; C1 ; 8 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; C2 ; 9 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; C3 ; 1 ; 2 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; ; C4 ; 0 ; 2 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; ; C5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; C6 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; C7 ; 315 ; 3 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; ; C8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; C9 ; 310 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; C10 ; 296 ; 3 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; ; C11 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; C12 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; C13 ; 275 ; 4 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; ; C14 ; 260 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; C15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; C16 ; 254 ; 4 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; ; C17 ; 245 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; C18 ; 244 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; C19 ; 238 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; C20 ; 239 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; C21 ; 236 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; C22 ; 237 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; D1 ; 14 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; D2 ; 15 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; D3 ; 2 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; D4 ; 3 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; D5 ; 4 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; D6 ; 5 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; D7 ; 311 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; D8 ; 309 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; D9 ; 302 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; D10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; D11 ; 289 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; D12 ; 284 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; ; D13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; D14 ; 267 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; D15 ; 259 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; D16 ; 255 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; D17 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; D18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; D19 ; 240 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; D20 ; 241 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; D21 ; 229 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; D22 ; 230 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; E1 ; 20 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; E2 ; 21 ; 2 ; HEX0[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; E3 ; 6 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; E4 ; 7 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; E5 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; E6 ; ; ; VCCA_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; E7 ; 316 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; E8 ; 308 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; E9 ; 301 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; E10 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; E11 ; 288 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; E12 ; 285 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; ; E13 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; E14 ; 266 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; E15 ; 256 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; E16 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; ; E17 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; ; E18 ; 243 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; E19 ; 242 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; E20 ; 234 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; E21 ; 227 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; E22 ; 228 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; F1 ; 22 ; 2 ; HEX0[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; F2 ; 23 ; 2 ; HEX0[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; F3 ; 13 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; F4 ; 10 ; 2 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; ; F5 ; ; ; GND_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ; ; F6 ; ; ; GND_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ; ; F7 ; ; ; GNDA_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ; ; F8 ; 312 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; F9 ; 307 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; F10 ; 295 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; F11 ; 294 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; F12 ; 276 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; F13 ; 269 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; F14 ; 268 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; F15 ; 262 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; F16 ; ; ; VCCA_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; F17 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; F18 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; ; F19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; F20 ; 235 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; F21 ; 223 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; F22 ; 224 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; G1 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; G2 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; G3 ; 16 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; G4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; G5 ; 12 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; G6 ; 11 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; G7 ; 317 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; G8 ; 313 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; G9 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; G10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; G11 ; 291 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; G12 ; 277 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; G13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; G14 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; G15 ; 261 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; G16 ; 252 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; G17 ; 231 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; G18 ; 232 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; G19 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; G20 ; 233 ; 5 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; ; G21 ; 221 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; G22 ; 222 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; H1 ; 24 ; 2 ; HEX0[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; H2 ; 25 ; 2 ; HEX0[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; H3 ; 27 ; 2 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; ; H4 ; 17 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; H5 ; 18 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; H6 ; 19 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; H7 ; 318 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; H8 ; 314 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; H9 ; 300 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; H10 ; 299 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; H11 ; 290 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; H12 ; 274 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; H13 ; 263 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; H14 ; 257 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; H15 ; 253 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; H16 ; 219 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; H17 ; 226 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; H18 ; 225 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; H19 ; 214 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; H20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; H21 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; H22 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; J1 ; 29 ; 2 ; HEX0[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; J2 ; 30 ; 2 ; HEX0[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; J3 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; J4 ; 28 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; J5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; J6 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; J7 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; J8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; J9 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; J10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; J11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; J12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; J13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; J14 ; 258 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; J15 ; 220 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; J16 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; J17 ; 218 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; J18 ; 217 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; J19 ; 216 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; J20 ; 213 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; J21 ; 211 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; J22 ; 212 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; K1 ; 37 ; 2 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; ; K2 ; 32 ; 2 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; ; K3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; K4 ; 36 ; 2 ; ^DATA0 ; input ; ; ; -- ; ; -- ; -- ; ; K5 ; 31 ; 2 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; ; K6 ; 33 ; 2 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; ; K7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; K8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; K9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; K11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; K13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; K14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; K15 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; K16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; K17 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; K18 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; K19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; K20 ; 215 ; 5 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; ; K21 ; 209 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; K22 ; 210 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; L1 ; 38 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; ; L2 ; 39 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; ; L3 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; L4 ; 40 ; 2 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; ; L5 ; 34 ; 2 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; ; L6 ; 35 ; 2 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ; ; L7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; L8 ; 26 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; L9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; L10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; L12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; L14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; L15 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; L16 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; L17 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; L18 ; 208 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; L19 ; 207 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; L20 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; L21 ; 205 ; 5 ; SW[1] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; L22 ; 206 ; 5 ; SW[0] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; M1 ; 41 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; ; M2 ; 42 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; ; M3 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; M4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; M5 ; 43 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; M6 ; 44 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; M7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; M8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; M9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; M11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; M13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; M14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; M15 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; M16 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; M17 ; 198 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; ; M18 ; 202 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; M19 ; 201 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; M20 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; M21 ; 203 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; ; M22 ; 204 ; 6 ; SW[2] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; N1 ; 45 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; N2 ; 46 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; N3 ; 51 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; N4 ; 52 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; N5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; N6 ; 49 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; N7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; N8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; N9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; N10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; N12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; N14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; N15 ; 194 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; N16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; N17 ; 197 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; ; N18 ; 196 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; ; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; N20 ; 195 ; 6 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; ; N21 ; 199 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; N22 ; 200 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; P1 ; 47 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; P2 ; 48 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; P3 ; 50 ; 1 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; ; P4 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; P5 ; 55 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; P6 ; 56 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; P7 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; P8 ; 95 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; P9 ; 94 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; P10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; P11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; P12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; P13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; P14 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; P15 ; 193 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; P16 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; P17 ; 186 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; P18 ; 187 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; P19 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; P20 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; P21 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; P22 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; R1 ; 57 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; R2 ; 58 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; R3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; R4 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; R5 ; 63 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; R6 ; 64 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; R7 ; 54 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; R8 ; 53 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; R9 ; 109 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; R10 ; 108 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; R11 ; 116 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; R12 ; 134 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; R13 ; 145 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; R14 ; 150 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; R15 ; 151 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; R16 ; 155 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; R17 ; 177 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; R18 ; 184 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; R19 ; 185 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; R20 ; 192 ; 6 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; ; R21 ; 190 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; R22 ; 191 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; T1 ; 59 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; T2 ; 60 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; T3 ; 69 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; T4 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; T5 ; 67 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; T6 ; 68 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; T7 ; 91 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; T8 ; 90 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; T9 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; T11 ; 115 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; T12 ; 131 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; T13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; T14 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; T15 ; 147 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; T16 ; 156 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; T17 ; ; ; GND_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ; ; T18 ; 171 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; T19 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; T21 ; 188 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; T22 ; 189 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; U1 ; 61 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; U2 ; 62 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; U3 ; 70 ; 1 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; ; U4 ; 80 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; U5 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; ; U6 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; U7 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; U8 ; 92 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; U9 ; 106 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; U10 ; 107 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; U11 ; 123 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; ; U12 ; 124 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; ; U13 ; 132 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; U14 ; 146 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; U15 ; 157 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; U16 ; ; ; VCCA_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; U17 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; U18 ; 170 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; U19 ; 172 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; U20 ; 176 ; 6 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; ; U21 ; 182 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; U22 ; 183 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; V1 ; 65 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; V2 ; 66 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; V3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; V4 ; 81 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; V5 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; ; V6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; V7 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; ; V8 ; 98 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; V9 ; 101 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; V10 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; V11 ; 118 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; V12 ; 126 ; 7 ; SW[3] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; ; V13 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; V14 ; 142 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; V15 ; 158 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; V16 ; ; ; GNDA_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ; ; V17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; V18 ; ; ; GND_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ; ; V19 ; 166 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; V20 ; 173 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; V21 ; 180 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; V22 ; 181 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; W1 ; 71 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; W2 ; 72 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; W3 ; 75 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; W4 ; 76 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; W5 ; 79 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; W6 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; W7 ; 99 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; W8 ; 100 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; W9 ; 105 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; W10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; W11 ; 117 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; W12 ; 125 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; ; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; W14 ; 141 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; W15 ; 149 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; W16 ; 160 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; W17 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; W18 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; W19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; W20 ; 167 ; 6 ; ~LVDS91p/nCEO~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; ; W21 ; 174 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; W22 ; 175 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; Y1 ; 73 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; Y2 ; 74 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; Y3 ; 77 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; Y4 ; 78 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; Y5 ; 86 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; Y6 ; 87 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; Y7 ; 93 ; 8 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; ; Y8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; Y9 ; 104 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; Y10 ; 112 ; 8 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; ; Y11 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; Y12 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; Y13 ; 133 ; 7 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; ; Y14 ; 148 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; Y16 ; 154 ; 7 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; ; Y17 ; 159 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; Y18 ; 165 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; Y19 ; 168 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; Y20 ; 169 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; Y21 ; 178 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; Y22 ; 179 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ Note: Pin directions (input, output or bidir) are based on device operating in user mode. +-------------------------------------------------------------------------------+ ; Output Pin Default Load For Reported TCO ; +----------------------------------+-------+------------------------------------+ ; I/O Standard ; Load ; Termination Resistance ; +----------------------------------+-------+------------------------------------+ ; 3.3-V LVTTL ; 0 pF ; Not Available ; ; 3.3-V LVCMOS ; 0 pF ; Not Available ; ; 2.5 V ; 0 pF ; Not Available ; ; 1.8 V ; 0 pF ; Not Available ; ; 1.5 V ; 0 pF ; Not Available ; ; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ; ; 3.3-V PCI-X ; 10 pF ; 25 Ohm (Parallel) ; ; SSTL-2 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; ; SSTL-2 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; ; SSTL-18 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; ; SSTL-18 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; ; 1.5-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; ; 1.5-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; ; 1.8-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; ; 1.8-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; ; Differential SSTL-2 ; 0 pF ; (See SSTL-2) ; ; Differential 2.5-V SSTL Class II ; 0 pF ; (See SSTL-2 Class II) ; ; Differential 1.8-V SSTL Class I ; 0 pF ; (See 1.8-V SSTL Class I) ; ; Differential 1.8-V SSTL Class II ; 0 pF ; (See 1.8-V SSTL Class II) ; ; Differential 1.5-V HSTL Class I ; 0 pF ; (See 1.5-V HSTL Class I) ; ; Differential 1.5-V HSTL Class II ; 0 pF ; (See 1.5-V HSTL Class II) ; ; Differential 1.8-V HSTL Class I ; 0 pF ; (See 1.8-V HSTL Class I) ; ; Differential 1.8-V HSTL Class II ; 0 pF ; (See 1.8-V HSTL Class II) ; ; LVDS ; 0 pF ; 100 Ohm (Differential) ; ; mini-LVDS ; 0 pF ; 100 Ohm (Differential) ; ; RSDS ; 0 pF ; 100 Ohm (Differential) ; ; Simple RSDS ; 0 pF ; Not Available ; ; Differential LVPECL ; 0 pF ; 100 Ohm (Differential) ; +----------------------------------+-------+------------------------------------+ Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables. +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Fitter Resource Utilization by Entity ; +----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------------------------+--------------+ ; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ; +----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------------------------+--------------+ ; |7seg_sw_hex ; 7 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 11 ; 0 ; 7 (0) ; 0 (0) ; 0 (0) ; |7seg_sw_hex ; work ; ; |7seg:inst| ; 7 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (0) ; 0 (0) ; 0 (0) ; |7seg_sw_hex|7seg:inst ; work ; ; |7seg012:inst| ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 0 (0) ; |7seg_sw_hex|7seg:inst|7seg012:inst ; work ; ; |7seg3456:inst1| ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 0 (0) ; |7seg_sw_hex|7seg:inst|7seg3456:inst1 ; work ; +----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------------------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. +----------------------------------------------------------------------------------+ ; Delay Chain Summary ; +---------+----------+---------------+---------------+-----------------------+-----+ ; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; +---------+----------+---------------+---------------+-----------------------+-----+ ; HEX0[6] ; Output ; -- ; -- ; -- ; -- ; ; HEX0[5] ; Output ; -- ; -- ; -- ; -- ; ; HEX0[4] ; Output ; -- ; -- ; -- ; -- ; ; HEX0[3] ; Output ; -- ; -- ; -- ; -- ; ; HEX0[2] ; Output ; -- ; -- ; -- ; -- ; ; HEX0[1] ; Output ; -- ; -- ; -- ; -- ; ; HEX0[0] ; Output ; -- ; -- ; -- ; -- ; ; SW[2] ; Input ; (0) 171 ps ; (0) 171 ps ; -- ; -- ; ; SW[0] ; Input ; (0) 171 ps ; (0) 171 ps ; -- ; -- ; ; SW[1] ; Input ; (0) 171 ps ; (0) 171 ps ; -- ; -- ; ; SW[3] ; Input ; (0) 170 ps ; (0) 170 ps ; -- ; -- ; +---------+----------+---------------+---------------+-----------------------+-----+ +---------------------------------------------------+ ; Pad To Core Delay Chain Fanout ; +---------------------+-------------------+---------+ ; Source Pin / Fanout ; Pad To Core Index ; Setting ; +---------------------+-------------------+---------+ ; SW[2] ; ; ; ; SW[0] ; ; ; ; SW[1] ; ; ; ; SW[3] ; ; ; +---------------------+-------------------+---------+ +---------------------------------------------+ ; Non-Global High Fan-Out Signals ; +-----------------------------------+---------+ ; Name ; Fan-Out ; +-----------------------------------+---------+ ; SW[3] ; 7 ; ; SW[1] ; 7 ; ; SW[0] ; 7 ; ; SW[2] ; 7 ; ; 7seg:inst|7seg012:inst|seg0~0 ; 1 ; ; 7seg:inst|7seg012:inst|seg1~0 ; 1 ; ; 7seg:inst|7seg012:inst|seg2~0 ; 1 ; ; 7seg:inst|7seg3456:inst1|inst9~0 ; 1 ; ; 7seg:inst|7seg3456:inst1|inst12~0 ; 1 ; ; 7seg:inst|7seg3456:inst1|inst17~0 ; 1 ; ; 7seg:inst|7seg3456:inst1|inst21~0 ; 1 ; +-----------------------------------+---------+ +-----------------------------------------------------+ ; Other Routing Usage Summary ; +-----------------------------+-----------------------+ ; Other Routing Resource Type ; Usage ; +-----------------------------+-----------------------+ ; Block interconnects ; 11 / 54,004 ( < 1 % ) ; ; C16 interconnects ; 2 / 2,100 ( < 1 % ) ; ; C4 interconnects ; 7 / 36,000 ( < 1 % ) ; ; Direct links ; 2 / 54,004 ( < 1 % ) ; ; Global clocks ; 0 / 16 ( 0 % ) ; ; Local interconnects ; 0 / 18,752 ( 0 % ) ; ; R24 interconnects ; 7 / 1,900 ( < 1 % ) ; ; R4 interconnects ; 9 / 46,920 ( < 1 % ) ; +-----------------------------+-----------------------+ +--------------------------------------------------------------------------+ ; LAB Logic Elements ; +--------------------------------------------+-----------------------------+ ; Number of Logic Elements (Average = 7.00) ; Number of LABs (Total = 1) ; +--------------------------------------------+-----------------------------+ ; 1 ; 0 ; ; 2 ; 0 ; ; 3 ; 0 ; ; 4 ; 0 ; ; 5 ; 0 ; ; 6 ; 0 ; ; 7 ; 1 ; ; 8 ; 0 ; ; 9 ; 0 ; ; 10 ; 0 ; ; 11 ; 0 ; ; 12 ; 0 ; ; 13 ; 0 ; ; 14 ; 0 ; ; 15 ; 0 ; ; 16 ; 0 ; +--------------------------------------------+-----------------------------+ +---------------------------------------------------------------------------+ ; LAB Signals Sourced ; +---------------------------------------------+-----------------------------+ ; Number of Signals Sourced (Average = 7.00) ; Number of LABs (Total = 1) ; +---------------------------------------------+-----------------------------+ ; 0 ; 0 ; ; 1 ; 0 ; ; 2 ; 0 ; ; 3 ; 0 ; ; 4 ; 0 ; ; 5 ; 0 ; ; 6 ; 0 ; ; 7 ; 1 ; +---------------------------------------------+-----------------------------+ +-------------------------------------------------------------------------------+ ; LAB Signals Sourced Out ; +-------------------------------------------------+-----------------------------+ ; Number of Signals Sourced Out (Average = 7.00) ; Number of LABs (Total = 1) ; +-------------------------------------------------+-----------------------------+ ; 0 ; 0 ; ; 1 ; 0 ; ; 2 ; 0 ; ; 3 ; 0 ; ; 4 ; 0 ; ; 5 ; 0 ; ; 6 ; 0 ; ; 7 ; 1 ; +-------------------------------------------------+-----------------------------+ +---------------------------------------------------------------------------+ ; LAB Distinct Inputs ; +---------------------------------------------+-----------------------------+ ; Number of Distinct Inputs (Average = 4.00) ; Number of LABs (Total = 1) ; +---------------------------------------------+-----------------------------+ ; 0 ; 0 ; ; 1 ; 0 ; ; 2 ; 0 ; ; 3 ; 0 ; ; 4 ; 1 ; +---------------------------------------------+-----------------------------+ +-------------------------------------------------------------------------+ ; Fitter Device Options ; +----------------------------------------------+--------------------------+ ; Option ; Setting ; +----------------------------------------------+--------------------------+ ; Enable user-supplied start-up clock (CLKUSR) ; Off ; ; Enable device-wide reset (DEV_CLRn) ; Off ; ; Enable device-wide output enable (DEV_OE) ; Off ; ; Enable INIT_DONE output ; Off ; ; Configuration scheme ; Active Serial ; ; Error detection CRC ; Off ; ; nCEO ; As output driving ground ; ; ASDO,nCSO ; As input tri-stated ; ; Reserve all unused pins ; As output driving ground ; ; Base pin-out file on sameframe device ; Off ; +----------------------------------------------+--------------------------+ +------------------------------------+ ; Operating Settings and Conditions ; +---------------------------+--------+ ; Setting ; Value ; +---------------------------+--------+ ; Nominal Core Voltage ; 1.20 V ; ; Low Junction Temperature ; 0 °C ; ; High Junction Temperature ; 85 °C ; +---------------------------+--------+ +-----------------+ ; Fitter Messages ; +-----------------+ Info (11104): Parallel Compilation has detected 4 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 2 of the 2 physical processors detected instead. Info (119006): Selected device EP2C20F484C7 for design "V1" Info (21077): Low junction temperature is 0 degrees C Info (21077): High junction temperature is 85 degrees C Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices Info (176445): Device EP2C15AF484C7 is compatible Info (176445): Device EP2C35F484C7 is compatible Info (176445): Device EP2C50F484C7 is compatible Info (169124): Fitter converted 3 user pins into dedicated programming pins Info (169125): Pin ~ASDO~ is reserved at location C4 Info (169125): Pin ~nCSO~ is reserved at location C3 Info (169125): Pin ~LVDS91p/nCEO~ is reserved at location W20 Critical Warning (332012): Synopsys Design Constraints File file not found: 'V1.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. Info (332144): No user constrained base clocks found in the design Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. Warning (332068): No clocks defined in design. Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. Info (176233): Starting register packing Warning (176250): Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. Info (176235): Finished register packing Extra Info (176219): No registers were packed into other blocks Warning (15709): Ignored I/O standard assignments to the following nodes Warning (15710): Ignored I/O standard assignment to node "AUD_ADCDAT" Warning (15710): Ignored I/O standard assignment to node "AUD_ADCLRCK" Warning (15710): Ignored I/O standard assignment to node "AUD_BCLK" Warning (15710): Ignored I/O standard assignment to node "AUD_DACDAT" Warning (15710): Ignored I/O standard assignment to node "AUD_DACLRCK" Warning (15710): Ignored I/O standard assignment to node "AUD_XCK" Warning (15710): Ignored I/O standard assignment to node "CLOCK_24[0]" Warning (15710): Ignored I/O standard assignment to node "CLOCK_24[1]" Warning (15710): Ignored I/O standard assignment to node "CLOCK_27[1]" Warning (15710): Ignored I/O standard assignment to node "CLOCK_50" Warning (15710): Ignored I/O standard assignment to node "EXT_CLOCK" Warning (15710): Ignored I/O standard assignment to node "GPIO_0[0]" Warning (15710): Ignored I/O standard assignment to node "GPIO_0[10]" Warning (15710): Ignored I/O standard assignment to node "GPIO_0[11]" Warning (15710): Ignored I/O standard assignment to node "GPIO_0[12]" Warning (15710): Ignored I/O standard assignment to node "GPIO_0[13]" Warning (15710): Ignored I/O standard assignment to node "GPIO_0[14]" Warning (15710): Ignored I/O standard assignment to node "GPIO_0[15]" Warning (15710): Ignored I/O standard assignment to node "GPIO_0[16]" Warning (15710): Ignored I/O standard assignment to node "GPIO_0[17]" Warning (15710): Ignored I/O standard assignment to node "GPIO_0[18]" Warning (15710): Ignored I/O standard assignment to node "GPIO_0[19]" Warning (15710): Ignored I/O standard assignment to node "GPIO_0[1]" Warning (15710): Ignored I/O standard assignment to node "GPIO_0[20]" Warning (15710): Ignored I/O standard assignment to node "GPIO_0[21]" Warning (15710): Ignored I/O standard assignment to node "GPIO_0[22]" Warning (15710): Ignored I/O standard assignment to node "GPIO_0[23]" Warning (15710): Ignored I/O standard assignment to node "GPIO_0[24]" Warning (15710): Ignored I/O standard assignment to node "GPIO_0[25]" Warning (15710): Ignored I/O standard assignment to node "GPIO_0[26]" Warning (15710): Ignored I/O standard assignment to node "GPIO_0[27]" Warning (15710): Ignored I/O standard assignment to node "GPIO_0[28]" Warning (15710): Ignored I/O standard assignment to node "GPIO_0[29]" Warning (15710): Ignored I/O standard assignment to node "GPIO_0[2]" Warning (15710): Ignored I/O standard assignment to node "GPIO_0[30]" Warning (15710): Ignored I/O standard assignment to node "GPIO_0[31]" Warning (15710): Ignored I/O standard assignment to node "GPIO_0[32]" Warning (15710): Ignored I/O standard assignment to node "GPIO_0[33]" Warning (15710): Ignored I/O standard assignment to node "GPIO_0[34]" Warning (15710): Ignored I/O standard assignment to node "GPIO_0[35]" Warning (15710): Ignored I/O standard assignment to node "GPIO_0[3]" Warning (15710): Ignored I/O standard assignment to node "GPIO_0[4]" Warning (15710): Ignored I/O standard assignment to node "GPIO_0[5]" Warning (15710): Ignored I/O standard assignment to node "GPIO_0[6]" Warning (15710): Ignored I/O standard assignment to node "GPIO_0[7]" Warning (15710): Ignored I/O standard assignment to node "GPIO_0[8]" Warning (15710): Ignored I/O standard assignment to node "GPIO_0[9]" Warning (15710): Ignored I/O standard assignment to node "GPIO_1[0]" Warning (15710): Ignored I/O standard assignment to node "GPIO_1[10]" Warning (15710): Ignored I/O standard assignment to node "GPIO_1[11]" Warning (15710): Ignored I/O standard assignment to node "GPIO_1[12]" Warning (15710): Ignored I/O standard assignment to node "GPIO_1[13]" Warning (15710): Ignored I/O standard assignment to node "GPIO_1[14]" Warning (15710): Ignored I/O standard assignment to node "GPIO_1[15]" Warning (15710): Ignored I/O standard assignment to node "GPIO_1[16]" Warning (15710): Ignored I/O standard assignment to node "GPIO_1[17]" Warning (15710): Ignored I/O standard assignment to node "GPIO_1[18]" Warning (15710): Ignored I/O standard assignment to node "GPIO_1[19]" Warning (15710): Ignored I/O standard assignment to node "GPIO_1[1]" Warning (15710): Ignored I/O standard assignment to node "GPIO_1[20]" Warning (15710): Ignored I/O standard assignment to node "GPIO_1[21]" Warning (15710): Ignored I/O standard assignment to node "GPIO_1[22]" Warning (15710): Ignored I/O standard assignment to node "GPIO_1[23]" Warning (15710): Ignored I/O standard assignment to node "GPIO_1[24]" Warning (15710): Ignored I/O standard assignment to node "GPIO_1[25]" Warning (15710): Ignored I/O standard assignment to node "GPIO_1[26]" Warning (15710): Ignored I/O standard assignment to node "GPIO_1[27]" Warning (15710): Ignored I/O standard assignment to node "GPIO_1[28]" Warning (15710): Ignored I/O standard assignment to node "GPIO_1[29]" Warning (15710): Ignored I/O standard assignment to node "GPIO_1[2]" Warning (15710): Ignored I/O standard assignment to node "GPIO_1[30]" Warning (15710): Ignored I/O standard assignment to node "GPIO_1[31]" Warning (15710): Ignored I/O standard assignment to node "GPIO_1[32]" Warning (15710): Ignored I/O standard assignment to node "GPIO_1[33]" Warning (15710): Ignored I/O standard assignment to node "GPIO_1[34]" Warning (15710): Ignored I/O standard assignment to node "GPIO_1[35]" Warning (15710): Ignored I/O standard assignment to node "GPIO_1[3]" Warning (15710): Ignored I/O standard assignment to node "GPIO_1[4]" Warning (15710): Ignored I/O standard assignment to node "GPIO_1[5]" Warning (15710): Ignored I/O standard assignment to node "GPIO_1[6]" Warning (15710): Ignored I/O standard assignment to node "GPIO_1[7]" Warning (15710): Ignored I/O standard assignment to node "GPIO_1[8]" Warning (15710): Ignored I/O standard assignment to node "GPIO_1[9]" Warning (15710): Ignored I/O standard assignment to node "HEX1[0]" Warning (15710): Ignored I/O standard assignment to node "HEX1[1]" Warning (15710): Ignored I/O standard assignment to node "HEX1[2]" Warning (15710): Ignored I/O standard assignment to node "HEX1[3]" Warning (15710): Ignored I/O standard assignment to node "HEX1[4]" Warning (15710): Ignored I/O standard assignment to node "HEX1[5]" Warning (15710): Ignored I/O standard assignment to node "HEX1[6]" Warning (15710): Ignored I/O standard assignment to node "HEX2[0]" Warning (15710): Ignored I/O standard assignment to node "HEX2[1]" Warning (15710): Ignored I/O standard assignment to node "HEX2[2]" Warning (15710): Ignored I/O standard assignment to node "HEX2[3]" Warning (15710): Ignored I/O standard assignment to node "HEX2[4]" Warning (15710): Ignored I/O standard assignment to node "HEX2[5]" Warning (15710): Ignored I/O standard assignment to node "HEX2[6]" Warning (15710): Ignored I/O standard assignment to node "HEX3[0]" Warning (15710): Ignored I/O standard assignment to node "HEX3[1]" Warning (15710): Ignored I/O standard assignment to node "HEX3[2]" Warning (15710): Ignored I/O standard assignment to node "HEX3[3]" Warning (15710): Ignored I/O standard assignment to node "HEX3[4]" Warning (15710): Ignored I/O standard assignment to node "HEX3[5]" Warning (15710): Ignored I/O standard assignment to node "HEX3[6]" Warning (15710): Ignored I/O standard assignment to node "I2C_SCLK" Warning (15710): Ignored I/O standard assignment to node "I2C_SDAT" Warning (15710): Ignored I/O standard assignment to node "KEY[0]" Warning (15710): Ignored I/O standard assignment to node "KEY[1]" Warning (15710): Ignored I/O standard assignment to node "KEY[2]" Warning (15710): Ignored I/O standard assignment to node "KEY[3]" Warning (15710): Ignored I/O standard assignment to node "LEDG[0]" Warning (15710): Ignored I/O standard assignment to node "LEDG[1]" Warning (15710): Ignored I/O standard assignment to node "LEDG[2]" Warning (15710): Ignored I/O standard assignment to node "LEDG[3]" Warning (15710): Ignored I/O standard assignment to node "LEDG[4]" Warning (15710): Ignored I/O standard assignment to node "LEDG[5]" Warning (15710): Ignored I/O standard assignment to node "LEDG[6]" Warning (15710): Ignored I/O standard assignment to node "LEDG[7]" Warning (15710): Ignored I/O standard assignment to node "LEDR[0]" Warning (15710): Ignored I/O standard assignment to node "LEDR[1]" Warning (15710): Ignored I/O standard assignment to node "LEDR[2]" Warning (15710): Ignored I/O standard assignment to node "LEDR[3]" Warning (15710): Ignored I/O standard assignment to node "LEDR[4]" Warning (15710): Ignored I/O standard assignment to node "LEDR[5]" Warning (15710): Ignored I/O standard assignment to node "LEDR[6]" Warning (15710): Ignored I/O standard assignment to node "LEDR[7]" Warning (15710): Ignored I/O standard assignment to node "LEDR[8]" Warning (15710): Ignored I/O standard assignment to node "LEDR[9]" Warning (15710): Ignored I/O standard assignment to node "PS2_CLK" Warning (15710): Ignored I/O standard assignment to node "PS2_DAT" Warning (15710): Ignored I/O standard assignment to node "SW[4]" Warning (15710): Ignored I/O standard assignment to node "SW[5]" Warning (15710): Ignored I/O standard assignment to node "SW[6]" Warning (15710): Ignored I/O standard assignment to node "SW[7]" Warning (15710): Ignored I/O standard assignment to node "SW[8]" Warning (15710): Ignored I/O standard assignment to node "SW[9]" Warning (15710): Ignored I/O standard assignment to node "TCK" Warning (15710): Ignored I/O standard assignment to node "TCS" Warning (15710): Ignored I/O standard assignment to node "TDI" Warning (15710): Ignored I/O standard assignment to node "TDO" Warning (15710): Ignored I/O standard assignment to node "UART_RXD" Warning (15710): Ignored I/O standard assignment to node "UART_TXD" Warning (15710): Ignored I/O standard assignment to node "VGA_B[0]" Warning (15710): Ignored I/O standard assignment to node "VGA_B[1]" Warning (15710): Ignored I/O standard assignment to node "VGA_B[2]" Warning (15710): Ignored I/O standard assignment to node "VGA_B[3]" Warning (15710): Ignored I/O standard assignment to node "VGA_G[0]" Warning (15710): Ignored I/O standard assignment to node "VGA_G[1]" Warning (15710): Ignored I/O standard assignment to node "VGA_G[2]" Warning (15710): Ignored I/O standard assignment to node "VGA_G[3]" Warning (15710): Ignored I/O standard assignment to node "VGA_HS" Warning (15710): Ignored I/O standard assignment to node "VGA_R[0]" Warning (15710): Ignored I/O standard assignment to node "VGA_R[1]" Warning (15710): Ignored I/O standard assignment to node "VGA_R[2]" Warning (15710): Ignored I/O standard assignment to node "VGA_R[3]" Warning (15710): Ignored I/O standard assignment to node "VGA_VS" Warning (15705): Ignored locations or region assignments to the following nodes Warning (15706): Node "AUD_ADCDAT" is assigned to location or region, but does not exist in design Warning (15706): Node "AUD_ADCLRCK" is assigned to location or region, but does not exist in design Warning (15706): Node "AUD_BCLK" is assigned to location or region, but does not exist in design Warning (15706): Node "AUD_DACDAT" is assigned to location or region, but does not exist in design Warning (15706): Node "AUD_DACLRCK" is assigned to location or region, but does not exist in design Warning (15706): Node "AUD_XCK" is assigned to location or region, but does not exist in design Warning (15706): Node "CLOCK_24[0]" is assigned to location or region, but does not exist in design Warning (15706): Node "CLOCK_24[1]" is assigned to location or region, but does not exist in design Warning (15706): Node "CLOCK_27[0]" is assigned to location or region, but does not exist in design Warning (15706): Node "CLOCK_27[1]" is assigned to location or region, but does not exist in design Warning (15706): Node "CLOCK_50" is assigned to location or region, but does not exist in design Warning (15706): Node "DRAM_ADDR[0]" is assigned to location or region, but does not exist in design Warning (15706): Node "DRAM_ADDR[10]" is assigned to location or region, but does not exist in design Warning (15706): Node "DRAM_ADDR[11]" is assigned to location or region, but does not exist in design Warning (15706): Node "DRAM_ADDR[1]" is assigned to location or region, but does not exist in design Warning (15706): Node "DRAM_ADDR[2]" is assigned to location or region, but does not exist in design Warning (15706): Node "DRAM_ADDR[3]" is assigned to location or region, but does not exist in design Warning (15706): Node "DRAM_ADDR[4]" is assigned to location or region, but does not exist in design Warning (15706): Node "DRAM_ADDR[5]" is assigned to location or region, but does not exist in design Warning (15706): Node "DRAM_ADDR[6]" is assigned to location or region, but does not exist in design Warning (15706): Node "DRAM_ADDR[7]" is assigned to location or region, but does not exist in design Warning (15706): Node "DRAM_ADDR[8]" is assigned to location or region, but does not exist in design Warning (15706): Node "DRAM_ADDR[9]" is assigned to location or region, but does not exist in design Warning (15706): Node "DRAM_BA_0" is assigned to location or region, but does not exist in design Warning (15706): Node "DRAM_BA_1" is assigned to location or region, but does not exist in design Warning (15706): Node "DRAM_CAS_N" is assigned to location or region, but does not exist in design Warning (15706): Node "DRAM_CKE" is assigned to location or region, but does not exist in design Warning (15706): Node "DRAM_CLK" is assigned to location or region, but does not exist in design Warning (15706): Node "DRAM_CS_N" is assigned to location or region, but does not exist in design Warning (15706): Node "DRAM_DQ[0]" is assigned to location or region, but does not exist in design Warning (15706): Node "DRAM_DQ[10]" is assigned to location or region, but does not exist in design Warning (15706): Node "DRAM_DQ[11]" is assigned to location or region, but does not exist in design Warning (15706): Node "DRAM_DQ[12]" is assigned to location or region, but does not exist in design Warning (15706): Node "DRAM_DQ[13]" is assigned to location or region, but does not exist in design Warning (15706): Node "DRAM_DQ[14]" is assigned to location or region, but does not exist in design Warning (15706): Node "DRAM_DQ[15]" is assigned to location or region, but does not exist in design Warning (15706): Node "DRAM_DQ[1]" is assigned to location or region, but does not exist in design Warning (15706): Node "DRAM_DQ[2]" is assigned to location or region, but does not exist in design Warning (15706): Node "DRAM_DQ[3]" is assigned to location or region, but does not exist in design Warning (15706): Node "DRAM_DQ[4]" is assigned to location or region, but does not exist in design Warning (15706): Node "DRAM_DQ[5]" is assigned to location or region, but does not exist in design Warning (15706): Node "DRAM_DQ[6]" is assigned to location or region, but does not exist in design Warning (15706): Node "DRAM_DQ[7]" is assigned to location or region, but does not exist in design Warning (15706): Node "DRAM_DQ[8]" is assigned to location or region, but does not exist in design Warning (15706): Node "DRAM_DQ[9]" is assigned to location or region, but does not exist in design Warning (15706): Node "DRAM_LDQM" is assigned to location or region, but does not exist in design Warning (15706): Node "DRAM_RAS_N" is assigned to location or region, but does not exist in design Warning (15706): Node "DRAM_UDQM" is assigned to location or region, but does not exist in design Warning (15706): Node "DRAM_WE_N" is assigned to location or region, but does not exist in design Warning (15706): Node "EXT_CLOCK" is assigned to location or region, but does not exist in design Warning (15706): Node "FL_ADDR[0]" is assigned to location or region, but does not exist in design Warning (15706): Node "FL_ADDR[10]" is assigned to location or region, but does not exist in design Warning (15706): Node "FL_ADDR[11]" is assigned to location or region, but does not exist in design Warning (15706): Node "FL_ADDR[12]" is assigned to location or region, but does not exist in design Warning (15706): Node "FL_ADDR[13]" is assigned to location or region, but does not exist in design Warning (15706): Node "FL_ADDR[14]" is assigned to location or region, but does not exist in design Warning (15706): Node "FL_ADDR[15]" is assigned to location or region, but does not exist in design Warning (15706): Node "FL_ADDR[16]" is assigned to location or region, but does not exist in design Warning (15706): Node "FL_ADDR[17]" is assigned to location or region, but does not exist in design Warning (15706): Node "FL_ADDR[18]" is assigned to location or region, but does not exist in design Warning (15706): Node "FL_ADDR[19]" is assigned to location or region, but does not exist in design Warning (15706): Node "FL_ADDR[1]" is assigned to location or region, but does not exist in design Warning (15706): Node "FL_ADDR[20]" is assigned to location or region, but does not exist in design Warning (15706): Node "FL_ADDR[21]" is assigned to location or region, but does not exist in design Warning (15706): Node "FL_ADDR[2]" is assigned to location or region, but does not exist in design Warning (15706): Node "FL_ADDR[3]" is assigned to location or region, but does not exist in design Warning (15706): Node "FL_ADDR[4]" is assigned to location or region, but does not exist in design Warning (15706): Node "FL_ADDR[5]" is assigned to location or region, but does not exist in design Warning (15706): Node "FL_ADDR[6]" is assigned to location or region, but does not exist in design Warning (15706): Node "FL_ADDR[7]" is assigned to location or region, but does not exist in design Warning (15706): Node "FL_ADDR[8]" is assigned to location or region, but does not exist in design Warning (15706): Node "FL_ADDR[9]" is assigned to location or region, but does not exist in design Warning (15706): Node "FL_DQ[0]" is assigned to location or region, but does not exist in design Warning (15706): Node "FL_DQ[1]" is assigned to location or region, but does not exist in design Warning (15706): Node "FL_DQ[2]" is assigned to location or region, but does not exist in design Warning (15706): Node "FL_DQ[3]" is assigned to location or region, but does not exist in design Warning (15706): Node "FL_DQ[4]" is assigned to location or region, but does not exist in design Warning (15706): Node "FL_DQ[5]" is assigned to location or region, but does not exist in design Warning (15706): Node "FL_DQ[6]" is assigned to location or region, but does not exist in design Warning (15706): Node "FL_DQ[7]" is assigned to location or region, but does not exist in design Warning (15706): Node "FL_OE_N" is assigned to location or region, but does not exist in design Warning (15706): Node "FL_RST_N" is assigned to location or region, but does not exist in design Warning (15706): Node "FL_WE_N" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_0[0]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_0[10]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_0[11]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_0[12]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_0[13]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_0[14]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_0[15]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_0[16]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_0[17]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_0[18]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_0[19]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_0[1]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_0[20]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_0[21]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_0[22]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_0[23]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_0[24]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_0[25]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_0[26]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_0[27]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_0[28]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_0[29]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_0[2]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_0[30]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_0[31]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_0[32]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_0[33]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_0[34]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_0[35]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_0[3]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_0[4]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_0[5]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_0[6]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_0[7]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_0[8]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_0[9]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_1[0]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_1[10]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_1[11]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_1[12]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_1[13]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_1[14]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_1[15]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_1[16]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_1[17]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_1[18]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_1[19]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_1[1]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_1[20]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_1[21]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_1[22]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_1[23]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_1[24]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_1[25]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_1[26]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_1[27]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_1[28]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_1[29]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_1[2]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_1[30]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_1[31]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_1[32]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_1[33]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_1[34]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_1[35]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_1[3]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_1[4]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_1[5]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_1[6]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_1[7]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_1[8]" is assigned to location or region, but does not exist in design Warning (15706): Node "GPIO_1[9]" is assigned to location or region, but does not exist in design Warning (15706): Node "HEX1[0]" is assigned to location or region, but does not exist in design Warning (15706): Node "HEX1[1]" is assigned to location or region, but does not exist in design Warning (15706): Node "HEX1[2]" is assigned to location or region, but does not exist in design Warning (15706): Node "HEX1[3]" is assigned to location or region, but does not exist in design Warning (15706): Node "HEX1[4]" is assigned to location or region, but does not exist in design Warning (15706): Node "HEX1[5]" is assigned to location or region, but does not exist in design Warning (15706): Node "HEX1[6]" is assigned to location or region, but does not exist in design Warning (15706): Node "HEX2[0]" is assigned to location or region, but does not exist in design Warning (15706): Node "HEX2[1]" is assigned to location or region, but does not exist in design Warning (15706): Node "HEX2[2]" is assigned to location or region, but does not exist in design Warning (15706): Node "HEX2[3]" is assigned to location or region, but does not exist in design Warning (15706): Node "HEX2[4]" is assigned to location or region, but does not exist in design Warning (15706): Node "HEX2[5]" is assigned to location or region, but does not exist in design Warning (15706): Node "HEX2[6]" is assigned to location or region, but does not exist in design Warning (15706): Node "HEX3[0]" is assigned to location or region, but does not exist in design Warning (15706): Node "HEX3[1]" is assigned to location or region, but does not exist in design Warning (15706): Node "HEX3[2]" is assigned to location or region, but does not exist in design Warning (15706): Node "HEX3[3]" is assigned to location or region, but does not exist in design Warning (15706): Node "HEX3[4]" is assigned to location or region, but does not exist in design Warning (15706): Node "HEX3[5]" is assigned to location or region, but does not exist in design Warning (15706): Node "HEX3[6]" is assigned to location or region, but does not exist in design Warning (15706): Node "I2C_SCLK" is assigned to location or region, but does not exist in design Warning (15706): Node "I2C_SDAT" is assigned to location or region, but does not exist in design Warning (15706): Node "KEY[0]" is assigned to location or region, but does not exist in design Warning (15706): Node "KEY[1]" is assigned to location or region, but does not exist in design Warning (15706): Node "KEY[2]" is assigned to location or region, but does not exist in design Warning (15706): Node "KEY[3]" is assigned to location or region, but does not exist in design Warning (15706): Node "LEDG[0]" is assigned to location or region, but does not exist in design Warning (15706): Node "LEDG[1]" is assigned to location or region, but does not exist in design Warning (15706): Node "LEDG[2]" is assigned to location or region, but does not exist in design Warning (15706): Node "LEDG[3]" is assigned to location or region, but does not exist in design Warning (15706): Node "LEDG[4]" is assigned to location or region, but does not exist in design Warning (15706): Node "LEDG[5]" is assigned to location or region, but does not exist in design Warning (15706): Node "LEDG[6]" is assigned to location or region, but does not exist in design Warning (15706): Node "LEDG[7]" is assigned to location or region, but does not exist in design Warning (15706): Node "LEDR[0]" is assigned to location or region, but does not exist in design Warning (15706): Node "LEDR[1]" is assigned to location or region, but does not exist in design Warning (15706): Node "LEDR[2]" is assigned to location or region, but does not exist in design Warning (15706): Node "LEDR[3]" is assigned to location or region, but does not exist in design Warning (15706): Node "LEDR[4]" is assigned to location or region, but does not exist in design Warning (15706): Node "LEDR[5]" is assigned to location or region, but does not exist in design Warning (15706): Node "LEDR[6]" is assigned to location or region, but does not exist in design Warning (15706): Node "LEDR[7]" is assigned to location or region, but does not exist in design Warning (15706): Node "LEDR[8]" is assigned to location or region, but does not exist in design Warning (15706): Node "LEDR[9]" is assigned to location or region, but does not exist in design Warning (15706): Node "PS2_CLK" is assigned to location or region, but does not exist in design Warning (15706): Node "PS2_DAT" is assigned to location or region, but does not exist in design Warning (15706): Node "SD_CLK" is assigned to location or region, but does not exist in design Warning (15706): Node "SD_CMD" is assigned to location or region, but does not exist in design Warning (15706): Node "SD_DAT" is assigned to location or region, but does not exist in design Warning (15706): Node "SD_DAT3" is assigned to location or region, but does not exist in design Warning (15706): Node "SRAM_ADDR[0]" is assigned to location or region, but does not exist in design Warning (15706): Node "SRAM_ADDR[10]" is assigned to location or region, but does not exist in design Warning (15706): Node "SRAM_ADDR[11]" is assigned to location or region, but does not exist in design Warning (15706): Node "SRAM_ADDR[12]" is assigned to location or region, but does not exist in design Warning (15706): Node "SRAM_ADDR[13]" is assigned to location or region, but does not exist in design Warning (15706): Node "SRAM_ADDR[14]" is assigned to location or region, but does not exist in design Warning (15706): Node "SRAM_ADDR[15]" is assigned to location or region, but does not exist in design Warning (15706): Node "SRAM_ADDR[16]" is assigned to location or region, but does not exist in design Warning (15706): Node "SRAM_ADDR[17]" is assigned to location or region, but does not exist in design Warning (15706): Node "SRAM_ADDR[1]" is assigned to location or region, but does not exist in design Warning (15706): Node "SRAM_ADDR[2]" is assigned to location or region, but does not exist in design Warning (15706): Node "SRAM_ADDR[3]" is assigned to location or region, but does not exist in design Warning (15706): Node "SRAM_ADDR[4]" is assigned to location or region, but does not exist in design Warning (15706): Node "SRAM_ADDR[5]" is assigned to location or region, but does not exist in design Warning (15706): Node "SRAM_ADDR[6]" is assigned to location or region, but does not exist in design Warning (15706): Node "SRAM_ADDR[7]" is assigned to location or region, but does not exist in design Warning (15706): Node "SRAM_ADDR[8]" is assigned to location or region, but does not exist in design Warning (15706): Node "SRAM_ADDR[9]" is assigned to location or region, but does not exist in design Warning (15706): Node "SRAM_CE_N" is assigned to location or region, but does not exist in design Warning (15706): Node "SRAM_DQ[0]" is assigned to location or region, but does not exist in design Warning (15706): Node "SRAM_DQ[10]" is assigned to location or region, but does not exist in design Warning (15706): Node "SRAM_DQ[11]" is assigned to location or region, but does not exist in design Warning (15706): Node "SRAM_DQ[12]" is assigned to location or region, but does not exist in design Warning (15706): Node "SRAM_DQ[13]" is assigned to location or region, but does not exist in design Warning (15706): Node "SRAM_DQ[14]" is assigned to location or region, but does not exist in design Warning (15706): Node "SRAM_DQ[15]" is assigned to location or region, but does not exist in design Warning (15706): Node "SRAM_DQ[1]" is assigned to location or region, but does not exist in design Warning (15706): Node "SRAM_DQ[2]" is assigned to location or region, but does not exist in design Warning (15706): Node "SRAM_DQ[3]" is assigned to location or region, but does not exist in design Warning (15706): Node "SRAM_DQ[4]" is assigned to location or region, but does not exist in design Warning (15706): Node "SRAM_DQ[5]" is assigned to location or region, but does not exist in design Warning (15706): Node "SRAM_DQ[6]" is assigned to location or region, but does not exist in design Warning (15706): Node "SRAM_DQ[7]" is assigned to location or region, but does not exist in design Warning (15706): Node "SRAM_DQ[8]" is assigned to location or region, but does not exist in design Warning (15706): Node "SRAM_DQ[9]" is assigned to location or region, but does not exist in design Warning (15706): Node "SRAM_LB_N" is assigned to location or region, but does not exist in design Warning (15706): Node "SRAM_OE_N" is assigned to location or region, but does not exist in design Warning (15706): Node "SRAM_UB_N" is assigned to location or region, but does not exist in design Warning (15706): Node "SRAM_WE_N" is assigned to location or region, but does not exist in design Warning (15706): Node "SW[4]" is assigned to location or region, but does not exist in design Warning (15706): Node "SW[5]" is assigned to location or region, but does not exist in design Warning (15706): Node "SW[6]" is assigned to location or region, but does not exist in design Warning (15706): Node "SW[7]" is assigned to location or region, but does not exist in design Warning (15706): Node "SW[8]" is assigned to location or region, but does not exist in design Warning (15706): Node "SW[9]" is assigned to location or region, but does not exist in design Warning (15706): Node "TCK" is assigned to location or region, but does not exist in design Warning (15706): Node "TCS" is assigned to location or region, but does not exist in design Warning (15706): Node "TDI" is assigned to location or region, but does not exist in design Warning (15706): Node "TDO" is assigned to location or region, but does not exist in design Warning (15706): Node "UART_RXD" is assigned to location or region, but does not exist in design Warning (15706): Node "UART_TXD" is assigned to location or region, but does not exist in design Warning (15706): Node "VGA_B[0]" is assigned to location or region, but does not exist in design Warning (15706): Node "VGA_B[1]" is assigned to location or region, but does not exist in design Warning (15706): Node "VGA_B[2]" is assigned to location or region, but does not exist in design Warning (15706): Node "VGA_B[3]" is assigned to location or region, but does not exist in design Warning (15706): Node "VGA_G[0]" is assigned to location or region, but does not exist in design Warning (15706): Node "VGA_G[1]" is assigned to location or region, but does not exist in design Warning (15706): Node "VGA_G[2]" is assigned to location or region, but does not exist in design Warning (15706): Node "VGA_G[3]" is assigned to location or region, but does not exist in design Warning (15706): Node "VGA_HS" is assigned to location or region, but does not exist in design Warning (15706): Node "VGA_R[0]" is assigned to location or region, but does not exist in design Warning (15706): Node "VGA_R[1]" is assigned to location or region, but does not exist in design Warning (15706): Node "VGA_R[2]" is assigned to location or region, but does not exist in design Warning (15706): Node "VGA_R[3]" is assigned to location or region, but does not exist in design Warning (15706): Node "VGA_VS" is assigned to location or region, but does not exist in design Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00 Info (170189): Fitter placement preparation operations beginning Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 Info (170193): Fitter routing operations beginning Info (170195): Router estimated average interconnect usage is 0% of the available device resources Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y14 to location X11_Y27 Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. Info (170201): Optimizations that may affect the design's routability were skipped Info (170200): Optimizations that may affect the design's timing were skipped Info (11888): Total time spent on timing analysis during the Fitter is 0.15 seconds. Info (306004): Started post-fitting delay annotation Warning (306006): Found 7 output pins without output pin load capacitance assignment Info (306007): Pin "HEX0[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info (306007): Pin "HEX0[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info (306007): Pin "HEX0[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info (306007): Pin "HEX0[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info (306007): Pin "HEX0[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info (306007): Pin "HEX0[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info (306007): Pin "HEX0[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info (306005): Delay annotation completed successfully Info (306004): Started post-fitting delay annotation Info (306005): Delay annotation completed successfully Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00 Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. Info (144001): Generated suppressed messages file /scratch/Versuch 1/output_files/V1.fit.smsg Info: Quartus II 64-Bit Fitter was successful. 0 errors, 435 warnings Info: Peak virtual memory: 701 megabytes Info: Processing ended: Wed Oct 21 16:40:50 2026 Info: Elapsed time: 00:00:07 Info: Total CPU time (on all processors): 00:00:05 +----------------------------+ ; Fitter Suppressed Messages ; +----------------------------+ The suppressed messages can be found in /scratch/Versuch 1/output_files/V1.fit.smsg.